Author: Day, D.S.
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TUPHA168 Improving Throughput and Latency of D-Bus to Meet the Requirements of the Fair Control System 809
  • D.S. Day, A. Hahn, C. Prados, M. Reese
    GSI, Darmstadt, Germany
  In developing the control system for the FAIR accelerator complex we encountered strict latency and throughput contraints on the timely supply of data to devices controlling ramped magnets. In addition, the timing hardware that interfaces to the White Rabbit timing network may be shared by multiple processes on a single front-end computer. This paper describes the interprocess communication and resource-sharing system, and the consequences of using the D-Bus message bus. Then our experience of improving latency and throughput performance to meet the realtime requirements of the control system is discussed. Work is also presented on prioritisation techniques to allow time-critical services to share the bus with other components.  
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