Author: Hanasz, S.
Paper Title Page
THPHA092 Optimisation of a Low-Noise 1.3 GHz PLL Frequency Synthesizer for the European XFEL 1595
  • S. Hanasz, K. Czuba, B. Gąsowski, L.Z. Zembala
    Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
  • H. Schlarb
    DESY, Hamburg, Germany
  Funding: Research supported by Polish Ministry of Science and Higher Education, founds for international co-financed projects for year 2017.
The Master Oscillator system of the European XFEL was built using frequency synthesis techniques that were found to have the best phase noise performance. This includes low noise frequency multipliers and non­multiplying phase lock loops, incorporated in the system to shape its output phase noise spectrum. Jitter of the output signal strongly depends on phase noise transmittance of the PLL and suboptimal design can worsen it by orders of magnitude. Taking into consideration that the PLL open loop transmittance usually can be shaped in multiple ways, and that the accurate phase noise measurements can easily take more than 30 minutes, designing an automated tool becomes a necessity. For this purpose an approach to the tuning system construction was chosen in order to make the phase noise optimisation process simpler. This paper describes the optimisation of PLL synthesizer phase noise, done to improve the performance of the European XFEL MO. We present the phase noise optimisation process and achieved results.
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