Hardware Technology
Paper Title Page
TUAPL01 MicroTCA Generic Data Acquisition Systems at ESS 118
  • S. Farina, J.H. Lee, J.P.S. Martins, D.P. Piso
    ESS, Lund, Sweden
  The European Spallation Source (ESS) is a Partnership of 17 European Nations committed to the goal of collectively building and operating the world's leading facility for research by use of neutrons by the second quarter of the 21st Century. The strive for innovation and the challenges that need to be overcome in order to achieve the requested performances pushed towards the adoption of one of the newest standards available on the market. ESS has decided to use MicroTCA as standard platform for the systems that require high data throughput and high uptime. The implications of this choice on the architecture of the systems will be described with emphasis on the data acquisition electronics.  
video icon Talk as video stream: https://youtu.be/warsqk8bwJs  
slides icon Slides TUAPL01 [1.663 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL01  
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TUAPL02 Porting VME-Based Optical-Link Remote I/O Module to a PLC Platform - An Approach to Maximize Cross-Platform Portability Using SoC 125
  • T. Masuda, A. Kiyomichi
    JASRI/SPring-8, Hyogo-ken, Japan
  The optical-link remote I/O system OPT-VME that consists of a VME master and several kinds of slave boards is widely used in SPring-8 and SACLA. As the next generation low-end platform instead of the outdated VMEbus, a Linux PLC such as Yokogawa e-RT3 has been considered. We have developed an e-RT3-based master module OPT-PLC to fully utilize a large number of existing remote boards. In the original system, low-level communication is performed by FPGA and high-level communication procedures are handled in the Solaris device driver on a VME CPU board. This driver becomes a barrier to port the system to e-RT3 platform. OPT-PLC should be handled by the e-RT3 standard driver in the same manner as other e-RT3 I/O modules. To solve the difficulty, OPT-PLC was equipped with Xilinx SoC and the high-level communication procedures were implemented as application software on ARM Linux in the SoC. As the result, OPT-PLC can be controlled through the standard e-RT3 driver. Furthermore, the system will be ported to other platform like PCI Express by replacing bus interface block in the PL part. This paper reports on our development as an approach to maximize cross-platform portability using SoC.  
video icon Talk as video stream: https://youtu.be/ci5-NHBCLWM  
slides icon Slides TUAPL02 [7.627 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL02  
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TUAPL03 Solving Vendor Lock-in in VME Single Board Computers through Open-sourcing of the PCIe-VME64x Bridge 131
  • G. Daniluk, J.D. Gonzalez Cobas, M. Suminski, A. Wujek
    CERN, Geneva, Switzerland
  • G. Gräbner, M. Miehling, T. Schnürer
    MEN, Nürnberg, Germany
  VME is a standard for modular electronics widely used in research institutes. Slave cards in a VME crate are controlled from a VME master, typically part of a Single Board Computer (SBC). The SBC typically runs an operating system and communicates with the VME bus through a PCI or PCIe-to-VME bridge chip. The de-facto standard bridge, TSI148, has recently been discontinued, and therefore the question arises about what bridging solution to use in new commercial SBC designs. This paper describes our effort to solve the VME bridge availability problem. Together with a commercial company, MEN, we have open-sourced their VHDL implementation of the PCIe-VME64x interface. We have created a new commodity which is free to be used in any SBC having an FPGA, thus avoiding vendor lock-in and providing a fertile ground for collaboration among institutes and companies around the VME platform. The article also describes the internals of the MEN PCIe-VME64x HDL core as well as the software package that comes with it.  
video icon Talk as video stream: https://youtu.be/rEbUntNO-_Q  
slides icon Slides TUAPL03 [15.891 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL03  
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TUAPL04 Em# Electrometer Comes to Light 137
  • J.A. Avila-Abellan, M. Broseta, G. Cuní, O. Matilla, M. Rodriguez, A. Ruz, J. Salabert, X. Serra-Gallifa
    ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain
  • A. Milan-Otero, P. Sjöblom
    MAX IV Laboratory, Lund University, Lund, Sweden
  Em# project is a collaboration project between MAX IV Laboratory and ALBA Synchrotron to obtain a high performant four-channel electrometer. Besides the objective of accurate current measurements down to the pico-ampere range, the project pursues to establish a reusable instrumentation platform with time stamped data collection able to perform real time calculations for flexible feedback implementations. The platform is based on a FPGA responsible of acquisition and synchronization where a real-time protocol between the modules has been implemented (Harmony) [*]. The data acquired is transmitted via PCIe to a Single Board Computer with an embedded Linux distribution where high level processing and synchronization with upper levels of Control System is executed. In this proceeding, the reasons that lead to start a complex instrument development instead of using a Commercial On the Shelf (COTS) solution will be discussed. The results of the produced units will be analyzed in terms of accuracy and processing capabilities. Finally, different Em# applications in particle accelerators will be described, further widening the functionality of the current state-of-the-art instrumentation.
[*] Present and Future of Harmony Bus, a Real-Time High Speed Bus for Data Transfer Between Fpga Cores, these proceedings
video icon Talk as video stream: https://youtu.be/UkZkXomW0nE  
slides icon Slides TUAPL04 [1.849 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL04  
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TUAPL05 PandABox: A Multipurpose Platform for Multi-technique Scanning and Feedback Applications 143
  • S. Zhang, Y.-M. Abiven, J. Bisou, F. Langlois, G. Renaud, F. Ta, G. Thibaux
    SOLEIL, Gif-sur-Yvette, France
  • M.G. Abbott, T.M. Cobb, C.J. Turner, I.S. Uzun
    DLS, Oxfordshire, United Kingdom
  • S.M. Minolli
    NEXEYA Systems, La Couronne, France
  PandABox is a development project resulting from a collaboration between Synchrotron SOLEIL and Diamond Light Source started in October 2015. The initial objective driving the project was to provide multi-channel encoder processing for synchronizing data acquisitions with motion systems in experimental continuous scans. The resulting system is a multi-purpose platform well adapted for multi-technique scanning and feedback applications. This flexible and modular platform embeds an industrial electronics board with a powerful Xilinx Zynq 7030 SoC (Avnet PicoZed), FMC slot, SFP module, TTL and LDVS I/Os and removable encoder peripheral modules. In the same manner, the firmware and software framework has been developed in a modular way to be easily configurable and adaptable. The whole system is open and extensible from the hardware level up to integration with control systems like TANGO or EPICS. This paper details the hardware capabilities, platform performance, framework adaptability, and the project status at both sites.
video icon Talk as video stream: https://youtu.be/uMQeg5HJZnw  
slides icon Slides TUAPL05 [2.878 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL05  
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TUAPL06 Cryomodule-on-Chip Simulation Engine 151
  • C. Serrano, L.R. Doolittle, V.K. Vytla
    LBNL, Berkeley, California, USA
  The Cryomodule-On-Chip (CMOC) simulation engine is a Verilog implementation of a cryomodule model used for Low-Level RF development for superconducting cavities. The model includes a state-space model of the accelerating fields inside a cavity, the mechanical resonances inside a cryomodule as well as their interactions. The implementation of the model along with the LLRF controller in the same FPGA allows for live simulations of an RF system. This allows for an interactive simulation framework, where emulated cavity signals are produced at the same rate as in a real system and therefore providing the opportunity to observe longer time-scale effects than in software simulations as well as a platform for software development and operator training.  
video icon Talk as video stream: https://youtu.be/gBhIzpEbZYU  
slides icon Slides TUAPL06 [3.929 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL06  
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TUMPL03 New EPICS/RTEMS IOC Based on Altera SOC at Jefferson Lab 304
  • J. Yan, T.L. Allison, B. Bevins, A. Cuffe, C. Seaton
    JLab, Newport News, Virginia, USA
  A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA was designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via u-boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDRs SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run the RTEMS and EPICS. The standard SoC IOC board would be mounted in a chassis and connected to a daughter card via a standard HSMC connector. The first design of the SoC IOC will be compatible with our current PC104 IOCs, which have been running on our accelerator control system for 10 years. Eventually, the standard SOC IOCS would be the next generation of low-level IOC for the Accelerator control at Jefferson Lab.
Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.
slides icon Slides TUMPL03 [1.094 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL03  
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TUPHA066 A Real-Time, Distributed Power Measuring and Transient Recording System for Accelerators' Electrical Networks 553
  • E. Freddi, O.Ø. Andreassen, K. Develle, J. Lahaye, I.T. Matasaho, A. Rijllart
    CERN, Geneva, Switzerland
  Particle accelerators are complex machines with fast and high power absorption peaks. Power quality is a critical aspect for correct operation. External and internal disturbances can have significant repercussions causing beam losses or severe perturbations. Mastering the load and understanding how network disturbances propagate across the network is a crucial step for developing the grid model and realizing the limits of the existing installations. Despite the fact that several off-the-shelf solutions for real time data acquisition are available, an in-house FPGA based solution was developed to create a distributed measurement system. The system can measure power and power quality on demand as well as acquire raw current and voltage data on a defined trigger, similar to a distributed oscilloscope. In addition, the system allows recording many digital signals from the high voltage switchgear enabling electrical perturbations to be easily correlated with the state of the network. The result is a scalable system with fully customizable software, written specifically for this purpose. The system prototype has been in service for two years and full-scale deployment is currently ongoing.  
poster icon Poster TUPHA066 [1.292 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA066  
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TUPHA068 FPGA-Based Pulsed-RF Phase and Amplitude Detector at SLRI 557
  • R. Rujanakraikarn
    SLRI, Nakhon Ratchasima, Thailand
  In this paper, the prototype of phase and amplitude detector for pulsed-RF measurement is described. The hardware is designed in VHDL and implemented using Field Programmable Gate Array (FPGA) for digital processing. The main phase and amplitude detection algorithm is implemented using state machine in the MicroBlaze soft processor. The detector system is designed to measure the phase and amplitude of a 5-microsecond wide 2,856 MHz pulsed-RF at a repetition rate of 0.5 Hz. The front-end hardware for the pulsed-RF signal acquisition is also described with the interface to the FPGA-based controller part. Initial test results of the prototype are presented.  
poster icon Poster TUPHA068 [3.645 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA068  
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TUPHA069 FPGA-Based Motion Control System for Medical Linear Accelerator Development at SLRI 562
  • R. Rujanakraikarn, P. Koonpong
    SLRI, Nakhon Ratchasima, Thailand
  Linear accelerator technology has been widely applied to radiotherapy machines and there has been an increasing demand of the machines in Thailand over the recent years. An attempt to increase the availability of the low-cost machines has been proposed for the domestic use purposes. Currently, the prototype of the 6 MeV medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI) in Nakorn Ratchasima, Thailand. For beam shaping purposes a so-called secondary collimator is utilized with different size arrangement of the collimator jaws. The collimator motion control is one of the necessary machine subsystems for producing the desired field size of the beam. In this paper, the FPGA-based motion control system of the machine prototype is presented. The programmable logic part of the hardware is designed in VHDL for digital processing. The main motion control algorithm is implemented in the main processor of Zedboard FPGA. Communication between the motion control subsystem and the main control system software of the machine is also described.  
poster icon Poster TUPHA069 [4.103 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA069  
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TUPHA070 Commissioning and Validation of the ATLAS Level-1 Topological Trigger 566
  • A.T. Aukerman, T.M. Hong
    University of Pittsburgh, Pittsburgh, Pennsylvania, USA
  The ATLAS experiment has recently commissioned a new hardware component of its first-level trigger: the topological processor (L1Topo). This innovative system, using state-of-the-art FPGA processors, selects events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Since the first-level trigger is a synchronous pipelined system, such requirements are applied within a latency of 200ns. We will present the first results from data recorded using the L1Topo trigger; these demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-pT leptons, including H->tau tau and J/Psi->mu mu. In addition, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize the performance of this new trigger system. To reach the required accuracy, the simulation must take into account the limited precision that can be achieved with kinematic calculations implemented in firmware.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA070  
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TUPHA071 Run Control Communication for the Upgrade of the ATLAS Muon-to-Central Trigger Processor Interface (MUCTPI) 571
  • R. Spiwoks, A. Armbruster, G. Carrillo-Montoya, M. Chelstowska, P. Czodrowski, P.-O. Deviveiros, T. Eifert, N. Ellis, P. Farthouat, G. Galster, S. Haas, L. Helary, O. Lagkas Nikolos, A. Marzin, T. Pauly, V. Ryjov, K. Schmieden, M. Silva Oliveira, J. Stelzer, P. Vichoudis, T. Wengler
    CERN, Geneva, Switzerland
  The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN will be upgraded to an ATCA blade system for Run 3. The new design requires development of new communication models for control, configuration and monitoring. A System-on-Chip (SoC) with a programmable logic part and a processor part will be used for communication to the run control system and to the MUCTPI processing FPGAs. Different approaches have been compared. First, we tried an available UDP-based implementation in firmware for the programmable logic. Although this approach works as expected, it does not provide any flexibility to extend the functionality to more complex operations, e.g. for serial protocols. Second, we used the SoC processor with an embedded Linux operating system and an application-specific software written in C++ using a TCP remote-procedure-call approach. The software is built and maintained using the Yocto/OpenEmbedded framework. This approach was successfully used to test and validate the MUCTPI prototype. A third approach under investigation is the option of porting the ATLAS run control software directly to the embedded Linux.  
poster icon Poster TUPHA071 [0.722 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA071  
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TUPHA072 Real-Time Liquid Scintillator Calibration Based on Intensity Modulated LED 575
  • F. Pollastrone, M. Riva
    ENEA C.R. Frascati, Frascati (Roma), Italy
  • G.C. Cardarilli
    Università degli Studi di Roma "Tor Vergata", Roma, Italy
  In many nuclear applications such as nuclear/high-energy physics and nuclear fusion, sensors are widely used in order to detect high energy particles. One of the available technologies is the scintillator, which is generally coupled with a photomultiplier and pulse amplifier. The detector acquisition chain is not stationary; mainly, it changes its gain as a function of the temperature and the nuclear irradiation on the photomultiplier; therefore it needs to be periodically calibrated during its operation. A calibration method reported in the literature is based on the use of a pulsed LED that flashes on the photomultiplier by generating a train of reference pulses. A new technique may be the use of an LED with continuous sinusoidal intensity emission. This provides as an output of the detector chain a small sinusoidal signal which can be digitally processed in real time, by measuring the gain and the delay time of the detector chain. Moreover, this sinusoidal background signal can be removed in real-time, before any processing or storage of data. This paper presents the technique, reporting its simulation and the main characteristics of the developed firmware and the hardware.  
poster icon Poster TUPHA072 [7.081 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA072  
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TUPHA073 RF Leakage Detector System 580
  • M. Jobs, K. Fransson, K.J. Gajewski
    Uppsala University, Uppsala, Sweden
  FREIA Laboratory is a new facility for developing and testing instrumentation for particle accelerators. There are two pulsed 400 kW 352 MHz RF sources, presently used for testing superconducting RF cavities and there is a need to monitor the electromagnetic field in the experimental hall. The RF leakage detector system consists of number of physically identical nodes with one of them configured as a master and the rest as slaves. Each node supports 3 separate RF measurement channels with a frequency span of 100 kHz to 1 GHz. A desired frequency band is selected using a front-end band-pass filter. The sensitivity of the sensor is -34 dBm and the dynamic range 48 dB. The slaves are battery powered for easy installation. Special care has been taken to minimize the power consumption resulting in battery life to be 4-13 months using 3xAAA batteries. The footprint of the module is 60x100x40 mm. The communication between the master and the slaves uses a Wireless Link operating at the 868 MHz ISM band. The system is controlled by EPICS using the StreamDevice driver. The master RF module is connected via an RS-232 line and a MOXA NPort server to the control system network.  
poster icon Poster TUPHA073 [2.344 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA073  
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TUPHA075 A MicroTCA based Beam Position Monitoring System at CRYRING@ESR 585
  • P.B. Miedzik, H. Bräuning, T. Hoffmann, A. Reiter, R. Singh
    GSI, Darmstadt, Germany
  At FAIR the commissioning of the re-assembled CRYRING accelerator, formerly hosted by Manne Siegbahn Laboratory Stockholm, is currently in progress. This compact low energy heavy ion synchrotron and experimental storage ring will be the main instrument for an extensive research programme [1] as well as a testing platform for the future beam instrumentation and control system concepts decided on for FAIR. Besides many other measurement systems CRYRING is equipped with 18 beam position monitors (BPM), for which a new data acquisition system (DAQ) was developed. Based on the upcoming MicroTCA form factor in combination with FPGA mezzanine card (FMC) technology the DAQ system was designed to be state-of-the-art, reliable, modular and of high performance. Testing 'Open Hardware', here the ADC FMCs and FMC carrier boards, was another intention of that concept. The DAQ layout and obstacles that had to be overcome as well as first measurements will be presented.  
poster icon Poster TUPHA075 [18.571 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA075  
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TUPHA079 Timing System Using FPGA for Medical Linear Accelerator Prototype at SLRI 589
  • P. Koonpong, R. Rujanakraikarn
    SLRI, Nakhon Ratchasima, Thailand
  A prototype of medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI). In order to maintain the proper operation of the machine, the pulse signal is used to synchronize the various subsystems such as electron gun, RF trigger, and magnetron trigger subsystems. In this project, we design the timing system using a XilinxSpartan-3 FPGA development board with VHDL in order to achieve the desired characteristics and sequences of the timing signals for those subsystems. A LabVIEW GUI is designed to interface with the timing system in order to control the time delay and pulse width via RS-232 serial interface. The results of the system design is achieved with the pulse resolution of a 20 nsec per step for four timing channels. The time delay and pulse width for each channel can be set independently based on the SYNC reference signal.  
poster icon Poster TUPHA079 [3.417 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA079  
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TUPHA080 New Data Acquisition System Implemented Based on MTCA.4 Form Factor for KSTAR Diagnostic System 593
  • T.G. Lee, J.S. Hong, G.I. Kwon, W.R. Lee, T.H. Tak
    NFRI, Daejon, Republic of Korea
  In Korea Superconducting Tokamak Advanced Research (KSTAR), various diagnostics systems were operated from the first plasma in 2008. Many diagnostic devices have been installed for measuring the various plasma properties such as plasma current, magnetic current, electron density, electron temperature, impurity, and so on. The DAQ system for measuring the various plasma properties were developed with various form factor digitizer such as VME, CPCI, PXI, VXI. and PCIe. These complicated form factors installed on KSTAR have difficulties with hardware management, software management and performance upgrades. In order to control real-time systems using several diagnostic signals, the real-time control system is required to share the data without delay between the diagnostic measurement system and the real-time control system without branch one signal. Therefore, we developed the Multifunction Control Unit (KMCU) as the standard control system MTCA.4 form-factor and implemented the various diagnostic DAQ system using KMCU V2, that is KMCU-Z30. This paper will present the implementation of KSTAR diagnostic DAQ systems configured with KMCU based on MTCA.4 and their operating results.  
poster icon Poster TUPHA080 [1.779 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA080  
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TUPHA081 Pilot Application of New Control System at SPring-8 RF Test Stand 597
  • N. Hosoda, M. Ishii, T. Ohshima, M. Yamaga
    JASRI/SPring-8, Hyogo-ken, Japan
  • T. Fukui
    RIKEN SPring-8 Center, Innovative Light Sources Division, Hyogo, Japan
  • A. Gimenez
    RIKEN, Japan
  After 20 years successful operation of SPring-8, the third generation synchrotron radiation facility, maintaining old analogue modules of LLRF system tend to be difficult. Meanwhile a digital technology like FPGA, fast ADC/DAC become popular. We decided to replace the old analog LLRF system with modern MTCA.4 based one. Prior to replacing the system, we planed to examine the performance of the new system at an RF test stand. An AMC digitizer and a RTM vector modulator were introduced. A feedback control function was reproduced in the FPGA of the digitizer. We also adopted EtherCAT for relatively slow control, such as a motor control for cavity tuner and monitoring of a vacuum pressure. In addition to developing the new hardware of MTCA.4, we were developing a new data acquisition system and a new MQTT based messaging system for an integrated control framework of SPring-8 and SACLA, the X-ray free electron laser facility. To prove feasibility of new control system, it was implemented at the RF test stand. As the result of high power RF operation, we achieved demanding stability of RF in the cavity. We also confirmed that new software framework was enough to control LLRF system.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA081  
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TUPHA213 Experience and Prospects of Real-Time Signal Processing and Representation for the Beam Diagnostics at COSY 970
  • I. Bekman, C. Böhme, V. Kamerdzhiev, S. Merzliakov, P. Niedermayer, K. Reimers, M. Simon, M. Thelen
    FZJ, Jülich, Germany
  Diagnostics of beam parameters is vital for the operation of any particle accelerator and contributes to the precision of the physics experiments. At COoler SYnchrotron of the Forschungszentrum Jülich there are several beam instrumentation subsystems with data acquired and processed in real-time for machine and operator use to ensure safe and efficient performance. Here are presented current development for the Beam Loss Monitor (BLM) with regard to usage of field programmable gate arrays (FPGAs) to achieve fast data processing and integration into the Experimental Physics and Industrial Control System (EPICS) used at COSY. Also presented is a way to create and run Graphical User Interfaces based on EPICS variables with Control System Studio (CSS) connected to a data archiving system to display and use previously collected data.  
poster icon Poster TUPHA213 [2.528 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA213  
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TUSH302 uSOP: An Embedded Linux Board for the Belle2 Detector Controls 1003
  • G. Tortone, A. Anastasio, V. Izzo
    INFN-Napoli, Napoli, Italy
  • A. Aloisio, F. Di Capua, R. Giordano
    University of Naples, Napoli, Italy
  • F. Ameli
    INFN-Roma1, Rome, Italy
  • P. Branchini
    roma3, Rome, Italy
  Control systems for scientific instruments and experiments would benefit from hardware and software platforms that provide flexible resources to fulfill various installation requirements. uSOP is a Single Board Computer based on ARM processor and Linux operating system that makes it possible to develop and deploy easily various control system frameworks (EPICS, Tango) supporting a variety of different buses (I2C, SPI, UART, JTAG), ADC, General Purpose and specialized digital IO. In this work we present a live demo of a uSOP board, showing a running IOC for a simple control task. We also describe the deployment of uSOP as a monitoring system architecture for the Belle2 experiment, presently under construction at the KEK Laboratory (Tsukuba, Japan).  
poster icon Poster TUSH302 [5.399 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUSH302  
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THMPL08 The SLAC Common-Platform Firmware for High-Performance Systems 1286
  • T. Straumann, R. Claus, J.M. D'Ewart, J.C. Frisch, G. Haller, R.T. Herbst, B. Hong, U. Legat, L. Ma, J.J. Olsen, B.A. Reese, R. Ruckman, L. Sapozhnikov, S.R. Smith, D. Van Winkle, J.A. Vásquez, M. Weaver, E. Williams, C. Xu, A. Young
    SLAC, Menlo Park, California, USA
  Funding: Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515
LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL08  
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THMPL09 VME Based Digitizers for Waveform Monitoring System of Linear Induction Accelerator (LIA-20) 1291
  • E.S. Kotov, A.M. Batrakov, G.A. Fatkin, A.V. Pavlenko, K.S. Shtro, M.Yu. Vasilyev
    BINP SB RAS, Novosibirsk, Russia
  • G.A. Fatkin, E.S. Kotov, A.V. Pavlenko, M.Yu. Vasilyev
    NSU, Novosibirsk, Russia
  Waveform monitoring system plays a special role in the control system of powerful pulse installations providing the most complete information about the installation functioning and its parameters. The report describes the family of VME modules used in the waveform monitoring system of a linear induction accelerator LIA-20. In order to organize inter-module synchronization the VME-64 bus extension implemented in the VME64-BINP crates is applied in the waveform digitizers.  
slides icon Slides THMPL09 [1.653 MB]  
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL09  
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THMPL10 New VME-Based Hardware for Automation in BINP 1294
  • G.A. Fatkin, A.O. Baluev, A.M. Batrakov, E.S. Kotov, Ya.M. Macheret, V.R. Mamkin, A. Panov, A.V. Pavlenko, A.N. Selivanov, M.Yu. Vasilyev
    BINP SB RAS, Novosibirsk, Russia
  • G.A. Fatkin, E.S. Kotov, A.V. Pavlenko, M.Yu. Vasilyev
    NSU, Novosibirsk, Russia
  A new VME-based crate and modules are presented in this work. This hardware is primarily intended for LIA-20 control system, but we also plane to use it for the upgrade of the controls of existing complexes such as: VEPP-2000, VEPP-4, VEPP-5 Preinjector. Modules were designed with an ability to be used planned projects such as Super c-tau factory. A crate is 6U VME64x compatible crate with additional synchronization, daisy-chain lines and 6U RIO-modules. Each crate has a built-in status monitoring over CAN-BUS with independent power supply. A family of VME modules is based on the same design sample and include: digitizers, timing modules, CAN-interface module, interlock module. All modules are cost effective and have TANGO device servers developed for them.  
slides icon Slides THMPL10 [7.378 MB]  
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL10  
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THPHA067 EtherCAT based DAQ system at ESS 1536
  • J. Etxeberria, J.H. Lee
    ESS, Lund, Sweden
  The European Spallation Source (ESS) is a multi-disciplinary research facility based on what will be the world's most powerful-pulsed neutron source. The Integrated Control System Division (ICS) is responsible of defining and providing control systems for the ESS facility. This control system will be based on the EPICS and it must be high performance, cost-efficient, safe, reliable and easily maintainable. At the same time there is a strong need for standardization. To fulfill these requirements ICS has chosen different hardware platforms, like MicroTCA, PLC, EtherCAT, etc. EtherCAT, a Ethernet-based real-time fieldbus will be analyzed, and different questions will be answered: -Why has EtherCAT been chosen? -In which cases is it deployed? -How is it integrated into EPICS? -What is the installation process? Along with data acquisition purposes, the ESS Motion Control and Automation Group decided to use EtherCAT hardware to develop an Open Source EtherCAT Master Motion Controller, for the control of all the actuators of the accelerator within the ESS project. Hence, an overview of the open Source Motion Controller and its integration in EPICS will be also presented.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA067  
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THPHA068 PandABlocks Open FPGA Framework and Web Stack 1539
  • C.J. Turner, M.G. Abbott, T.M. Cobb, I.J. Gillingham, I.S. Uzun
    DLS, Oxfordshire, United Kingdom
  • Y.-M. Abiven
    SOLEIL, Gif-sur-Yvette, France
  • G. Thibaux
    MEDIANE SYSTEM, Le Pecq, France
  PandABlocks is the open source firmware and software stack that powers PandABox, a Zynq SoC based "Position and Acquisition" platform for delivering triggers during multi-technique scanning. PandABlocks consists of a number of FPGA functional blocks that can be wired together at run-time according to application specific requirements. Status reporting and high speed data acquisition is handled by the onboard ARM processor and exposed via a TCP server with a protocol suitable for integration into control systems like "EPICS" or "TANGO". Also included in the framework is a webserver and web GUI to visualize and change the wiring of the blocks. The whole system adapts to the functional blocks present in the current FPGA build, allowing different FPGA firmware be created to support new FMC cards without rebuilding the TCP server and webserver. This paper details how the different layers of PandABlocks work together and how the system can be used to implement novel triggering applications.  
poster icon Poster THPHA068 [0.470 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA068  
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THPHA069 Control System for Atlas Tilecal HVremote Boards 1543
  • F. Martins, A. Gomes, L. Gurriana, A. Maio, L. Seabra
    LIP, Lisboa, Portugal
  • G.G. Evans, A. Gomes, A. Maio, C. Rato, J.M. Sabino, J.A. Soares Augusto
    FCUL, Lisboa, Portugal
  • G.G. Evans
    BioISI, Lisboa, Portugal
  • J.A. Soares Augusto
    Inesc-ID, Lisboa, Portugal
  Funding: Funding from FCT (Portuguese government funding agency of the MCTES); project "Colaboracão na Experiência ATLAS", CERN/FISNUC/0005/2015
One of the proposed solutions for upgrading the high voltage (HV) system of Tilecal, the ATLAS hadron calorimeter, consists in removing the HV regulation boards from the detector and deploying them in a low-radiation room where there is permanent access for maintenance. This option requires many ~100m long HV cables but removes the requirement of radiation hard boards. That solution simplifies the control system of the HV regulation cards (called HVRemote). It consists of a Detector Control System (DCS) node linked to 256 HVRemote boards through a tree of Ethernet connections. Each HVRemote includes a smart Ethernet transceiver for converting data and commands from the DCS into serial peripheral interface (SPI) signals routed to SPI-capable devices in the HVRemote. The DCS connection to the transceiver and the control of some SPI-capable devices via Ethernet has been tested successfully. It was fabricated a test board (HVRemote-ctrl) with the interfacing sub-system of the HVRemote. It is being tested through SPI-interfaces and several devices were already validated. A next version adds a few more ADC/DAC devices for checking their suitability for the final design.
poster icon Poster THPHA069 [0.404 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA069  
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THPHA070 Multiplexer for the Em# Electrometer 1548
  • P. Sjöblom, A. Milan-Otero, A.G. Persson
    MAX IV Laboratory, Lund University, Lund, Sweden
  Small currents need to be measured from a number of devices at a synchrotron and its beamlines. To meet this demand, MAX IV have joined a collaboration with ALBA to develop an electrometer that will ensure low current measurement capabilities and seamless integration into our Tango control system. The electrometers 4 independent channels can measure accurately in the fA range. Many devices produce larger currents and only need low sample rate. To make the electrometer more flexible, MAX IV have therefore developed a multiplexer with 8 independent channels. The multiplexer is both powered and controlled by the electrometer through its multipurpose IO interface. At most, an electrometer can control 4 multiplexers simultaneously giving a system with 32 channels, but the number of multiplexers can be chosen freely. The offset current introduced by the multiplexer is 45 pA and the noise is 3 pA. The offset is eliminated by settings in the electrometer. Current sweeps shows that currents steps as small as 10 pA can easily be measured and that switching time between channels before a steady signal is achieved is limited by the filter needed by the electrometer and not the multiplexer.  
poster icon Poster THPHA070 [8.675 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA070  
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THPHA071 Plans at CERN for Electronics and Communication in the Distributed I/O Tier 1552
  • G. Daniluk, E. Gousiou
    CERN, Geneva, Switzerland
  Controls and data acquisition in accelerators often involve some kind of computing platform (VME, PICMG 1.3, MTCA.4…) connected to Distributed I/O Tier electronics using a fieldbus or another kind of serial link. At CERN, we have started a project to rationalize this tier, providing a modular centrally-supported platform which allows equipment groups to focus on solving their particular problems while benefiting from a set of well-debugged building blocks. The paper describes the strategy, based on 3U Euro crates with a generic FPGA-based board featuring space for FMC mezzanines. Different mezzanines allow communication using different protocols. There are two variants of the electronics, to deploy in environments with and without radiation tolerance requirements. The plans we present are the result of extensive discussion at CERN among all stakeholders. We present them here with the aim of gathering further feedback and potential interest for inter-lab collaborations.  
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA071  
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THPHA072 A Position Encoder Processing Unit 1557
  • R. Hino, P. Fajardo, N. Janvier, T. Le Caër, F. Le Mentec
    ESRF, Grenoble, France
  Typical motion controllers rely on a feedback position encoder to detect the actuator output and correct for external factors. Recent advancements in positioning systems increased the demand for the ability to process a variety of sensors and use the result to feedback the motion controller. In addition, data acquisition tools are becoming essential for metrology purposes to diagnose and analyse the behaviour of the system. A multi-sensor, multi-protocol unit with processing and data acquisition capabilities has been developed to address these requirements. Here we describe the main features of this unit, its internal architecture, and few examples of application.  
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA072  
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THPHA075 FPGA-based BPM Data Acquisition for LCLS-II 1560
  • T. Straumann, S. L. Hoobler, J.J. Olsen, C. Xu, A. Young
    SLAC, Menlo Park, California, USA
  The LCLS-II facility currently under construction at SLAC will be capable of delivering an electron beam at a rate of up to almost 1MHz. The BPM system (and other diagnostics) are required to acquire time-stamped readings for each individual bunch. The high rate mandates that the processing algorithms as well as data exchange with other high-performance systems such as MPS (machine-protection system) or bunch-length monitors are implemented with FPGA technology. Our BPM-processing firmware builds on top of the SLAC "common-platform" [*] and integrates tightly with core services provided by the platform such as timing, data-buffering and communication channels.
* "The SLAC Common-Platform Firmware for High-Performance Systems"; submission #3014 to ICALEPCS 2017.
poster icon Poster THPHA075 [6.604 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA075  
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THPHA076 A Novel General Purpose Data Acquisition Board with a DIM Interface 1565
  • J. Jadlovsky, J. Cabala, A. Jadlovska, S. Jadlovska, M. Kopcik, M. Oravec, M. Tkacik, D. Voscek
    Technical University of Kosice, Kosice, Slovak Republic
  • P.Ch. Chochula, O. Pinazza
    CERN, Geneva, Switzerland
  A new general purpose data acquisition and control board (Board51) is presented in this paper. Board51 has primarily been developed for use in the ALICE experiment at CERN, but its open design allows for a wide use in any application requiring flexible and affordable data acquisition system. It provides analog I/O functionalities and is equipped with software bundle, allowing for easy integration into the SCADA. Based on the Silicon Labs C8051F350 MCU, the board features a fully-differential 24-bit ADC that provides an ability to perform very precise DAQ at sampling rate up to 1kHz. For analog outputs two 8-bit current-mode DACs can be used. Board51 is equipped with UART to USB interface that allows communication with any computer platform. As a result the board can be controlled through the DIM system. This is provided by a program running on a computer publishing services that include measured analog values of each ADC channel and accepts commands for setting ADC readout rate and DACs voltage. Digital inputs/outputs are also accessible using the DIM communication system. These services enable any computer on a common network to read measured values and control the board.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA076  
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THPHA079 Application of Soc Based Applications in the TPS Control System 1569
  • Y.-S. Cheng, K.T. Hsu, K.H. Hu, D. Lee, C.Y. Liao
    NSRRC, Hsinchu, Taiwan
  System on a chip (SoC) based system widely apply for accelerator control recently. These system with small footprint, low-cost with powerful CPU and rich interface solution to support many control applications. SoC based system running Linux operation system and EPICS IOC embedded to implement several applications. TPS (Taiwan Photon Source) adopts some SoC solutions in control system, includes alarm announcer, RadFET reader, frequency and divider control, power supply control, etc. The efforts for implementing are summarized in this paper.  
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA079  
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THPHA081 LO Board for 704.42 MHz Cavity Simulator for ESS 1573
  • I. Rutkowski, K. Czuba, M.G. Grzegrzolka
    Warsaw University of Technology, Institute of Electronic Systems, Warsaw, Poland
  Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2016/03
This paper describes the requirements, architecture, and measurements results of the local oscillator (LO) board prototype. The design will provide low phase noise clock and heterodyne signals for the 704.42 MHz Cavity Simulator for the European Spallation Source. A field detection has critical influence on the simulation's performance and its quality depends on the quality of the two aforementioned signals. The clock frequency is a subharmonic of the reference frequency and choice of the frequency divider generating the clock signals is discussed. The performance of selected dividers was compared. The LO frequency must be synthesized and frequency synthesis schemes are investigated. Critical components used in the direct analog scheme are identified and their selection criteria were given.
poster icon Poster THPHA081 [1.406 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA081  
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THPHA215 A Control Architecture Proposal for Sirius Beamlines 1947
  • M.A.L. Moraes, R.M. Caliari, R.R. Geraldes, G.B.Z.L. Moreno, J.R. Piton, L. Sanfelici, H.D. de Almeida
    LNLS, Campinas, Brazil
  With the increased performance provided by 4th generation synchrotron light sources, precise motion control and event synchronization are essential factors to ensure experiment resolution and performance. Many advanced beamline systems, such as a new high-dynamic double crystal monochromator (HD-DCM), are under development for Sirius, the new machine under construction in Brazil. Among the expected performance challenges in such applications, complex coordinated movements during flyscans/continuous scans, hardware synchronization for pump­-and-­probe experiments and active noise suppression are goals to be met. Two architectures are proposed to cover general-purpose and advanced applications. The HD-DCM controller was implemented in a MATLAB/Simulink environment, which is optimized for RCP. Hence, its software must be adapted to a more cost-effective platform. One candidate controller is the NI cRIO. The portability of both MATLAB and NI PXI, the present standard control platform at LNLS, codes to cRIO is evaluated in this paper. Control resolution, acquisition rates and other factors that might limit the performance of these advanced applications are also discussed.  
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DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA215  
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