TUAPL —  Hardware Technology   (10-Oct-17   09:30—11:00)
Chair: J. Serrano, CERN, Geneva, Switzerland
Paper Title Page
TUAPL01 MicroTCA Generic Data Acquisition Systems at ESS 118
  • S. Farina, J.H. Lee, J.P.S. Martins, D.P. Piso
    ESS, Lund, Sweden
  The European Spallation Source (ESS) is a Partnership of 17 European Nations committed to the goal of collectively building and operating the world's leading facility for research by use of neutrons by the second quarter of the 21st Century. The strive for innovation and the challenges that need to be overcome in order to achieve the requested performances pushed towards the adoption of one of the newest standards available on the market. ESS has decided to use MicroTCA as standard platform for the systems that require high data throughput and high uptime. The implications of this choice on the architecture of the systems will be described with emphasis on the data acquisition electronics.  
video icon Talk as video stream: https://youtu.be/warsqk8bwJs  
slides icon Slides TUAPL01 [1.663 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL01  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)  
TUAPL02 Porting VME-Based Optical-Link Remote I/O Module to a PLC Platform - An Approach to Maximize Cross-Platform Portability Using SoC 125
  • T. Masuda, A. Kiyomichi
    JASRI/SPring-8, Hyogo-ken, Japan
  The optical-link remote I/O system OPT-VME that consists of a VME master and several kinds of slave boards is widely used in SPring-8 and SACLA. As the next generation low-end platform instead of the outdated VMEbus, a Linux PLC such as Yokogawa e-RT3 has been considered. We have developed an e-RT3-based master module OPT-PLC to fully utilize a large number of existing remote boards. In the original system, low-level communication is performed by FPGA and high-level communication procedures are handled in the Solaris device driver on a VME CPU board. This driver becomes a barrier to port the system to e-RT3 platform. OPT-PLC should be handled by the e-RT3 standard driver in the same manner as other e-RT3 I/O modules. To solve the difficulty, OPT-PLC was equipped with Xilinx SoC and the high-level communication procedures were implemented as application software on ARM Linux in the SoC. As the result, OPT-PLC can be controlled through the standard e-RT3 driver. Furthermore, the system will be ported to other platform like PCI Express by replacing bus interface block in the PL part. This paper reports on our development as an approach to maximize cross-platform portability using SoC.  
video icon Talk as video stream: https://youtu.be/ci5-NHBCLWM  
slides icon Slides TUAPL02 [7.627 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL02  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)  
TUAPL03 Solving Vendor Lock-in in VME Single Board Computers through Open-sourcing of the PCIe-VME64x Bridge 131
  • G. Daniluk, J.D. Gonzalez Cobas, M. Suminski, A. Wujek
    CERN, Geneva, Switzerland
  • G. Gräbner, M. Miehling, T. Schnürer
    MEN, Nürnberg, Germany
  VME is a standard for modular electronics widely used in research institutes. Slave cards in a VME crate are controlled from a VME master, typically part of a Single Board Computer (SBC). The SBC typically runs an operating system and communicates with the VME bus through a PCI or PCIe-to-VME bridge chip. The de-facto standard bridge, TSI148, has recently been discontinued, and therefore the question arises about what bridging solution to use in new commercial SBC designs. This paper describes our effort to solve the VME bridge availability problem. Together with a commercial company, MEN, we have open-sourced their VHDL implementation of the PCIe-VME64x interface. We have created a new commodity which is free to be used in any SBC having an FPGA, thus avoiding vendor lock-in and providing a fertile ground for collaboration among institutes and companies around the VME platform. The article also describes the internals of the MEN PCIe-VME64x HDL core as well as the software package that comes with it.  
video icon Talk as video stream: https://youtu.be/rEbUntNO-_Q  
slides icon Slides TUAPL03 [15.891 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL03  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)  
TUAPL04 Em# Electrometer Comes to Light 137
  • J.A. Avila-Abellan, M. Broseta, G. Cuní, O. Matilla, M. Rodriguez, A. Ruz, J. Salabert, X. Serra-Gallifa
    ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain
  • A. Milan-Otero, P. Sjöblom
    MAX IV Laboratory, Lund University, Lund, Sweden
  Em# project is a collaboration project between MAX IV Laboratory and ALBA Synchrotron to obtain a high performant four-channel electrometer. Besides the objective of accurate current measurements down to the pico-ampere range, the project pursues to establish a reusable instrumentation platform with time stamped data collection able to perform real time calculations for flexible feedback implementations. The platform is based on a FPGA responsible of acquisition and synchronization where a real-time protocol between the modules has been implemented (Harmony) [*]. The data acquired is transmitted via PCIe to a Single Board Computer with an embedded Linux distribution where high level processing and synchronization with upper levels of Control System is executed. In this proceeding, the reasons that lead to start a complex instrument development instead of using a Commercial On the Shelf (COTS) solution will be discussed. The results of the produced units will be analyzed in terms of accuracy and processing capabilities. Finally, different Em# applications in particle accelerators will be described, further widening the functionality of the current state-of-the-art instrumentation.
[*] Present and Future of Harmony Bus, a Real-Time High Speed Bus for Data Transfer Between Fpga Cores, these proceedings
video icon Talk as video stream: https://youtu.be/UkZkXomW0nE  
slides icon Slides TUAPL04 [1.849 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL04  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)  
TUAPL05 PandABox: A Multipurpose Platform for Multi-technique Scanning and Feedback Applications 143
  • S. Zhang, Y.-M. Abiven, J. Bisou, F. Langlois, G. Renaud, F. Ta, G. Thibaux
    SOLEIL, Gif-sur-Yvette, France
  • M.G. Abbott, T.M. Cobb, C.J. Turner, I.S. Uzun
    DLS, Oxfordshire, United Kingdom
  • S.M. Minolli
    NEXEYA Systems, La Couronne, France
  PandABox is a development project resulting from a collaboration between Synchrotron SOLEIL and Diamond Light Source started in October 2015. The initial objective driving the project was to provide multi-channel encoder processing for synchronizing data acquisitions with motion systems in experimental continuous scans. The resulting system is a multi-purpose platform well adapted for multi-technique scanning and feedback applications. This flexible and modular platform embeds an industrial electronics board with a powerful Xilinx Zynq 7030 SoC (Avnet PicoZed), FMC slot, SFP module, TTL and LDVS I/Os and removable encoder peripheral modules. In the same manner, the firmware and software framework has been developed in a modular way to be easily configurable and adaptable. The whole system is open and extensible from the hardware level up to integration with control systems like TANGO or EPICS. This paper details the hardware capabilities, platform performance, framework adaptability, and the project status at both sites.
video icon Talk as video stream: https://youtu.be/uMQeg5HJZnw  
slides icon Slides TUAPL05 [2.878 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL05  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)  
TUAPL06 Cryomodule-on-Chip Simulation Engine 151
  • C. Serrano, L.R. Doolittle, V.K. Vytla
    LBNL, Berkeley, California, USA
  The Cryomodule-On-Chip (CMOC) simulation engine is a Verilog implementation of a cryomodule model used for Low-Level RF development for superconducting cavities. The model includes a state-space model of the accelerating fields inside a cavity, the mechanical resonances inside a cryomodule as well as their interactions. The implementation of the model along with the LLRF controller in the same FPGA allows for live simulations of an RF system. This allows for an interactive simulation framework, where emulated cavity signals are produced at the same rate as in a real system and therefore providing the opportunity to observe longer time-scale effects than in software simulations as well as a platform for software development and operator training.  
video icon Talk as video stream: https://youtu.be/gBhIzpEbZYU  
slides icon Slides TUAPL06 [3.929 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUAPL06  
Export • reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)